1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device which has a read bus line and a write bus line at the time of reading-out and writing operations or a bus line sharing reading-out and writing operations.
2. Description of the Related Art
A semiconductor memory device having a constitution shown in FIG. 1 has been heretofore known as a semiconductor memory device having a read bus line and a write bus line at the time of reading-out and writing operations or a bus line sharing reading-out and writing operations. FIG. 1 shows a constitution of the semiconductor memory device in which components from a memory cell to an I/O circuit are illustrated. The semiconductor memory device of FIG. 1 consists of memory cell arrays 611, 612, . . . , and 61m, sense amplifiers 621, 622, . . . , 62m, a write amplifier 63, a data amplifier 64, an I/O circuit 65, and a control circuit 66.
As shown in the circuit diagram of FIG. 2, for example, the control circuit 66 consists of two-input NAND circuits NA91 to NA9m and inverters INV911 to INV91m provided at each output of the NAND circuits NA91 to NA9m respectively. Sense amplifier selection signals Y61 to Y61m output from the inverters INV911 to INV91m are input to the sense amplifiers 621 to 62m as selection signals, respectively. The control circuit 66 controls by using the respective sense amplifier selection signals Y61 to Y6m so that only the sense amplifier connected to the memory cell array having a cell (objective cell ) performing data reading-out or writing operations operates.
Next, the reading-out operation of this conventional semiconductor memory device will be described with reference to the timing chart of FIG. 3.
For example, in a case where an objective cell is present in the cell array 611 of FIG. 1, at the time of data reading-out operation, only data YAD1 decoded from an address signal is made high in level immediately before a column address strobe (CAS) signal input to the control circuit 66 is made high in level as shown in FIG. 3. Data YAD2 to YADm decoded from other address signals remain low in level. For this reason, the sense amplifier selection signal Y61 output from the inverter INV911 is made high in level and the sense amplifier selection signals Y62 to Y6m output from other inverters INV912 to INV91m are made low in level, whereby only the sense amplifier 621 shown in FIG. 1 operates.
Thus, read-out data DT1 and DN1 of cell array 611 having an objective cell are amplified by the sense amplifier 621 and levels on the bus lines DB and XDB are changed as shown in FIG. 3. And, then data DT1 and DN1 are input to a data amplifier 64. Thereafter, they are output via the I/O circuit 65.
Next, an operation at the time of data writing will be described with reference to the timing chart of FIG. 4.
For example, in case where an objective cell is present in the cell array 611 of FIG. 1, at the time of data writing, after the input data is input to a write amplifier 63 via the I/O circuit 65 and it is amplified, the input data appears on the bus lines DB and XDB as shown in FIG. 4. Moreover, immediately before the CAS signal is made high in level as shown in FIG. 4, only the data YAD1 decoded from the address signal is made high in level, and the data YAD2 to YADm decoded from other address signals remain low in level. Therefore, as shown in FIG. 4, the sense amplifier selection signal YG1 output from the inverter INV911 is made high in level and the sense amplifier selection signals Y62 to Y6m are made low in level, and only the sense amplifier 621 shown in FIG. 1 operates. Thus, data DT1 and DN1 amplified by the sense amplifier 621 shown in FIG. 1 are written to the objective cell in the cell array 611.
FIG. 5 shows simulation results at the time of data writing operation in the conventional semiconductor device. The simulation results show the case where when data DT1 is high in level and data DN1 is low in level, data is output from the sense amplifier 621 whereby the data DT1 is made low in level and the data DN1 is made high in level. From FIG. 5, it can be seen that a time of 5.4 ns is required from the time of making sense amplifier selection signal Y61 high in level until lines of data DT1 and DN1 crosses.
However, in the conventional semiconductor memory device shown in FIG. 1, at the time of reading-out and writing operations, I/O data of m sense amplifiers 621 to 62m share a read bus line and a write bus line, or a bus line sharing one read-out and write-out. When the number of divisions of memory cells increases due to an increase in storage capacitance, wiring lengths of the bus lines DB and XDB increase so that the amount of data delay due to the wiring becomes larger. Particularly, when the semiconductor memory device is the dynamic random access memory according to the Rambus channel (Rambus DRAM) manufactured by Rambus corporation, which is able to transmit the data between microprocessor by a high speed of 500 Mbps, input and output of data must be on one side of a chip by reason of the package. Therefore, the amount of delay on the bus lines DB and XDB increases.
Furthermore, in order to cope with micronization of design rules and in order to save manufacturing cost, tungsten is sometimes used as wiring materials instead of aluminum. In this case, wiring resistance increases. In such circumstances, in the conventional semiconductor memory device shown in FIG. 1, the amount of delay due to the wiring further increases, whereby transmitting speeds of signals between the sense amplifiers 621 to 62m and the write amplifier 63 and the sense amplifiers 621 to 62m and the data amplifier 64 are decreased.
To solve such problems, a semiconductor memory device having an auxiliary sense amplifier on the read bus line is recited in Japanese Patent Application Laid Open No. 2-3168. FIG. 6 is a block diagram of an example of the semiconductor memory device recited in this gazette, which shows the constitution including the components from memory cells to output circuit. This semiconductor memory device consists of memory cell arrays 811, 812, . . . , and 81m, first sense amplifiers 821, 822, . . . , and 82m, a second sense amplifier 83, an output circuit 84, and a buffer amplifier 85. In the semiconductor memory device, a control operation is conducted, using sense amplifier selection signals Y81, Y82, . . . , and Y8m, such that only the first sense amplifier connected to a memory cell array in which an objective cell is present operates.
FIG. 7 shows a circuit diagram of an example of the buffer amplifier 85 in FIG. 6. As shown in FIG. 7, the buffer amplifier 85 consists of NMOS transistors Q91 and Q92 which operate upon receiving level changes of signal lines RB1 and XRB1 on their gates and an NMOS transistor Q93 receiving an enable signal BE on its gate to put buffer amplifier 85 into an operative state. The bus lines are divided into RB1 and XRB1, RB2 and XRB2 via the buffer amplifier 85.
Next, an operation of the conventional semiconductor memory device will be described. First, when an objective cell is present in the cell array 811, the first sense amplifier selection signal Y81 is made high in level, whereby the first sense amplifier 821 arranged corresponding to the cell array 811 operates. At this time, the enable signal BE of the buffer amplifier 85 is also made high in level so that the buffer amplifier 85 is put into an operative state.
Thus, after data of the cell array 811 having the objective cell is amplified by the first sense amplifier 821, the data appears as a potential difference on the bus lines RB1 and XRB1, and the potential difference is amplified by the buffer amplifier 85. The amplified data from the buffer amplifier 85 is supplied to the second sense amplifier 83 via the bus lines RB2 and XRB2 and is amplified further. Then, the data is output through the output circuit 84.
Next, when the objective cell is present in the cell array 81m, the first sense amplifier selection signal Y8m is made high in level by detecting the change in the address signal, and the first sense amplifier 82m arranged corresponding to the cell array 81m operates. At this time, the enable signal BE for the buffer amplifier 85 is low in level, so that the buffer amplifier 85 is put into the disable state.
Thus, data of the cell array 81m having the objective cell is amplified by the first sense amplifier 82m, and the amplified data is output on the bus lines RB2 and XRB2 as a potential difference. Next, the potential difference is amplified by the second sense amplifier 83, and the amplified potential difference is output through the output circuit 84. In this semiconductor memory device, the buffer amplifier 85 is arranged at an intermediate position on the shared read bus line, and the read bus line is divided into two parts. When the objective cell is present in the cell arrays from 81j to 81m, capacitance of the bus line can be made smaller compared to the case where the buffer amplifier 85 is not provided. Therefore, transmission speed of signals will be high.
In the conventional semiconductor memory device shown in FIG. 6, since the bus lines are separated by the buffer amplifier 85, wiring capacitance at the time of operations can be made small. However, timings of the sense amplifier selection signals Y81 to Y8m must be adjusted for the portion where the bus lines are separated. Furthermore, since the buffer amplifier 85 is provided, the bus lines can not be used both for reading-out and writing operations, so that the bus lines can not be used for shared bus lines.